On December 3, 2007, Samsung Electronics and Toshiba Corp. announced that they have licensed to one another, the product specifications and the rights to produce and market Samsung’s OneNAND and Flex-OneNAND, and Toshiba’s LBA-NAND and mobile LBA-NAND memory chips.
Both companies plan to develop compatible products based on the respective specifications to be released next year.
Our Take
After sitting on the sidelines and watching while ONFI amassed a membership roster of 57 companies since its establishment in May 2006, Samsung and Toshiba have finally acted and joined hands to develop products based on common specifications. Both companies are no strangers to collaboration, having shared common NAND specifications for years.
LBA-NAND, Toshiba’s solution for managing the increasing ECC requirements and bad block management of NAND flash by combining NAND flash memory with a controller in a single package, is expected to become mainstream for devices at 40nm and below. ONFI responded with their own version: BA-NAND. With Samsung’s backing, LBA-NAND is expected to be a very viable alternative to BA-NAND.
As for OneNAND, Samsung has been pressured by mobile phone manufacturers to license OneNAND to ensure a second source for the devices. Last year, Samsung licensed OneNAND to ST Microelectronics and now Toshiba. Toshiba and SanDisk (former M-Systems) jointly developed mDOC (mobile Disk-on-Chip) which is similar to OneNAND but based on MLC NAND. Both products integrate a NAND core, SRAM, error correcting engines, and logic circuits in a single chip with a NOR interface. In fact, OneNAND was developed by Samsung based on IP licensed from M-Systems with the licensing agreement subsequently terminated in 2005. mDOC has never been a significant product line for Toshiba and resource-wise, it does not make sense for Toshiba to invest in two similar but incompatible, competing solutions. It appears opting to support OneNAND at the expense of mDOC is the price Toshiba is willing to pay to garner Samsung’s backing for LBA-NAND.
Monday, December 3, 2007
Thursday, November 15, 2007
Spansion ORNAND2: NAND Or AND…
Spansion ORNAND2: NAND Or AND…
Spansion today announced the development of Mirrorbit ORNAND2, a new memory architecture employing Mirrorbit technology in a NAND memory array. Mirrorbit ORNAND2 will be introduced at the 45nm generation and targeted primarily at integrated data storage applications. Spansion claims the ORNAND2 requires 25 percent fewer mask layers than Spansion's 65nm MirrorBit ORNAND and offers “NAND-equivalent performance”.
Our Take
There are two areas where Spansion needs to take Mirrorbit ORNAND to be on a more equal footing with NAND in data storage applications.
1. Cost
2. Performance, particularly program performance.
Currently, the Mirrorbit cell size is around 8F2 versus 4F2 for NAND and ORNAND program performance is less than half that of MLC NAND. By scaling the current Mirrorbit ORNAND architecture, it would be difficult for ORNAND to make progress on either of these fronts, which is the reason for ORNAND2. So what exactly is ORNAND2?
Its use of Mirrorbit technology rules out SONOS NAND implementations such as Samsung’s TANOS and Macronix’s BE-SONOS. A cursory look at Spansion’s patent filings reveals they may be using a SONOS cell using inversion layers as bitlines. Hitachi and Renesas pioneered a similar concept in their floating gate-based AG-AND technology. The cell size of AG-AND was reduced dramatically from its AND predecessor by eliminating bitline diffusion and shallow trench isolation structures. Instead, an inversion layer formed by biasing an assist gate (AG) was used to form the source/drain regions. Programming was accomplished by source-side injection (SSI).
Spansion appears to have taken this concept and extended it to its Mirrorbit technology. The polysilicon floating gate has been replaced with a charge trapping layer, presumably ONO and the AG’s are now bitline gates. By employing SSI, two localized charges can be stored at opposite sides at the periphery of the cell.
The use of inversion-bitlines could potentially reduce the Mirrorbit cell size to 6F2. In addition, the greater electron efficiency of SSI versus CHE (channel hot electron injection) could provide a boost to the program performance. For example, AG-AND achieved a program performance of almost 10MB/s with 4-bank interleaving – comparable to MLC NAND.
Renesas stopped further development of AG-AND technology in 2005 and licensed production of the 90nm and 65nm product generations to Powerchip Semiconductor. PSC has, however, struggled to bring up the 90nm technology to high yields and has not made the transition to 65nm.
If Mirrorbit with inversion-bitlines is the approach Spansion has decided to take with Mirrorbit ORNAND2, it appears Spansion is confident it is able to overcome the challenges experienced by Renesas and PSC in ramping this technology in a high-volume manufacturing environment.
Spansion today announced the development of Mirrorbit ORNAND2, a new memory architecture employing Mirrorbit technology in a NAND memory array. Mirrorbit ORNAND2 will be introduced at the 45nm generation and targeted primarily at integrated data storage applications. Spansion claims the ORNAND2 requires 25 percent fewer mask layers than Spansion's 65nm MirrorBit ORNAND and offers “NAND-equivalent performance”.
Our Take
There are two areas where Spansion needs to take Mirrorbit ORNAND to be on a more equal footing with NAND in data storage applications.
1. Cost
2. Performance, particularly program performance.
Currently, the Mirrorbit cell size is around 8F2 versus 4F2 for NAND and ORNAND program performance is less than half that of MLC NAND. By scaling the current Mirrorbit ORNAND architecture, it would be difficult for ORNAND to make progress on either of these fronts, which is the reason for ORNAND2. So what exactly is ORNAND2?
Its use of Mirrorbit technology rules out SONOS NAND implementations such as Samsung’s TANOS and Macronix’s BE-SONOS. A cursory look at Spansion’s patent filings reveals they may be using a SONOS cell using inversion layers as bitlines. Hitachi and Renesas pioneered a similar concept in their floating gate-based AG-AND technology. The cell size of AG-AND was reduced dramatically from its AND predecessor by eliminating bitline diffusion and shallow trench isolation structures. Instead, an inversion layer formed by biasing an assist gate (AG) was used to form the source/drain regions. Programming was accomplished by source-side injection (SSI).
Spansion appears to have taken this concept and extended it to its Mirrorbit technology. The polysilicon floating gate has been replaced with a charge trapping layer, presumably ONO and the AG’s are now bitline gates. By employing SSI, two localized charges can be stored at opposite sides at the periphery of the cell.
The use of inversion-bitlines could potentially reduce the Mirrorbit cell size to 6F2. In addition, the greater electron efficiency of SSI versus CHE (channel hot electron injection) could provide a boost to the program performance. For example, AG-AND achieved a program performance of almost 10MB/s with 4-bank interleaving – comparable to MLC NAND.
Renesas stopped further development of AG-AND technology in 2005 and licensed production of the 90nm and 65nm product generations to Powerchip Semiconductor. PSC has, however, struggled to bring up the 90nm technology to high yields and has not made the transition to 65nm.
If Mirrorbit with inversion-bitlines is the approach Spansion has decided to take with Mirrorbit ORNAND2, it appears Spansion is confident it is able to overcome the challenges experienced by Renesas and PSC in ramping this technology in a high-volume manufacturing environment.
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