Tuesday, June 17, 2008

SanDisk and Toshiba to Jointly Develop 3D Memory

In a SEC filing today, SanDisk disclosed that it had signed a collaboration agreement with Toshiba for re-writeable 3D memory. Both companies will cross-license related IP to each other and SanDisk will receive licensing payments from Toshiba.

Investment for SanDisk-owned equipment which includes tooling for 3D R/W and 3D OTP memory is forecast to amount to $400 million in 2009 and $200 million in 2010.

The 3D R/W memory which consists of stacked vertical diode arrays shares most of the process modules and design architecture concepts with the 3D OTP memory. In the case of 3D OTP memory, four layers of stacked memory cells are in volume production at the 80nm node with 45nm currently under development.

A four level 3D R/W memory will have to at least catch up with NAND flash on process technology to be considered competitive with x4 NAND flash. This would put 3D R/W memory at least 3-4 years out. The other issue is whether an eight level stack is manufacturable at high yields. An eight-level stack was demonstrated by Matrix in 2003 on a much less advanced 0.25um geometry. Producing eight level memory stacks at leading edge technology is another matter.

Tuesday, June 3, 2008

Hynix Develops x3

Hynix announced it has developed a 32Gb 3-bit per cell NAND flash slated for production in October. Hynix stated that the 3-bit per cell technology would enable cost reductions of 30% over 2-bit per cell technology. The 32Gb chip is based on 48nm process technology.

Based on my estimates, the die size of this device should be over 200mm2, much larger than the 172mm2 of the recently announced 34nm 32Gb MLC NAND flash from Intel/Micron. It is unlikely the chip is using the All-Bitline architecture developed by SanDisk and Toshiba implying a fairly low program performance.

The 32Gb chip will probably be employed as a learning vehicle for applications enablement until a more competitive 41nm offering comes out next year.