Thursday, November 15, 2007

Spansion ORNAND2: NAND Or AND…

Spansion ORNAND2: NAND Or AND…

Spansion today announced the development of Mirrorbit ORNAND2, a new memory architecture employing Mirrorbit technology in a NAND memory array. Mirrorbit ORNAND2 will be introduced at the 45nm generation and targeted primarily at integrated data storage applications. Spansion claims the ORNAND2 requires 25 percent fewer mask layers than Spansion's 65nm MirrorBit ORNAND and offers “NAND-equivalent performance”.

Our Take
There are two areas where Spansion needs to take Mirrorbit ORNAND to be on a more equal footing with NAND in data storage applications.

1. Cost
2. Performance, particularly program performance.

Currently, the Mirrorbit cell size is around 8F2 versus 4F2 for NAND and ORNAND program performance is less than half that of MLC NAND. By scaling the current Mirrorbit ORNAND architecture, it would be difficult for ORNAND to make progress on either of these fronts, which is the reason for ORNAND2. So what exactly is ORNAND2?

Its use of Mirrorbit technology rules out SONOS NAND implementations such as Samsung’s TANOS and Macronix’s BE-SONOS. A cursory look at Spansion’s patent filings reveals they may be using a SONOS cell using inversion layers as bitlines. Hitachi and Renesas pioneered a similar concept in their floating gate-based AG-AND technology. The cell size of AG-AND was reduced dramatically from its AND predecessor by eliminating bitline diffusion and shallow trench isolation structures. Instead, an inversion layer formed by biasing an assist gate (AG) was used to form the source/drain regions. Programming was accomplished by source-side injection (SSI).

Spansion appears to have taken this concept and extended it to its Mirrorbit technology. The polysilicon floating gate has been replaced with a charge trapping layer, presumably ONO and the AG’s are now bitline gates. By employing SSI, two localized charges can be stored at opposite sides at the periphery of the cell.

The use of inversion-bitlines could potentially reduce the Mirrorbit cell size to 6F2. In addition, the greater electron efficiency of SSI versus CHE (channel hot electron injection) could provide a boost to the program performance. For example, AG-AND achieved a program performance of almost 10MB/s with 4-bank interleaving – comparable to MLC NAND.

Renesas stopped further development of AG-AND technology in 2005 and licensed production of the 90nm and 65nm product generations to Powerchip Semiconductor. PSC has, however, struggled to bring up the 90nm technology to high yields and has not made the transition to 65nm.

If Mirrorbit with inversion-bitlines is the approach Spansion has decided to take with Mirrorbit ORNAND2, it appears Spansion is confident it is able to overcome the challenges experienced by Renesas and PSC in ramping this technology in a high-volume manufacturing environment.