Hynix announced it has developed a 32Gb 3-bit per cell NAND flash slated for production in October. Hynix stated that the 3-bit per cell technology would enable cost reductions of 30% over 2-bit per cell technology. The 32Gb chip is based on 48nm process technology.
Based on my estimates, the die size of this device should be over 200mm2, much larger than the 172mm2 of the recently announced 34nm 32Gb MLC NAND flash from Intel/Micron. It is unlikely the chip is using the All-Bitline architecture developed by SanDisk and Toshiba implying a fairly low program performance.
The 32Gb chip will probably be employed as a learning vehicle for applications enablement until a more competitive 41nm offering comes out next year.
Showing posts with label 3-bit per cell. Show all posts
Showing posts with label 3-bit per cell. Show all posts
Tuesday, June 3, 2008
Monday, February 11, 2008
SanDisk's 3-Bit/Cell NAND Flash Technology Not a Short-Term Play
The development of a 16-gigabit 3-bit per cell (x3) NAND flash on 56-nanometer process technology by SanDisk and Toshiba offers the promise of further NAND flash memory cost reductions.
Due to higher design complexity, lower number of usable blocks and longer test times, x3 technology is expected to offer approximately 20% cost savings over comparable MLC devices at the same process generation.The key innovation of the x3 16Gb chip is the write performance of 8-megabytes per second (MB/s).
This outstanding performance is comparable to 5xnm MLC devices currently on the market and was enabled mainly through the development of an All Bit Line [ABL] architecture and advanced programming algorithms. ABL will also be deployed on all of SanDisk/Toshiba’s MLC devices boosting write performance to 34MB/s – comparable to SLC devices on the market.Alas, the full cost benefits of x3 won’t be realized for another two years, the reason being x3 is currently about one year behind MLC on the technology roadmap.
Nevertheless, Samsung and Intel - Micron Flash Technologies are expected to join the fray in 2008/9 and by 2012, 3-bit per cell NAND is forecast to account for 52.8% of NAND flash memory bits, followed by MLC NAND at 25.4%, 4-bit/cell NAND 16.6% and SLC NAND 4.4%.
Due to higher design complexity, lower number of usable blocks and longer test times, x3 technology is expected to offer approximately 20% cost savings over comparable MLC devices at the same process generation.The key innovation of the x3 16Gb chip is the write performance of 8-megabytes per second (MB/s).
This outstanding performance is comparable to 5xnm MLC devices currently on the market and was enabled mainly through the development of an All Bit Line [ABL] architecture and advanced programming algorithms. ABL will also be deployed on all of SanDisk/Toshiba’s MLC devices boosting write performance to 34MB/s – comparable to SLC devices on the market.Alas, the full cost benefits of x3 won’t be realized for another two years, the reason being x3 is currently about one year behind MLC on the technology roadmap.
Nevertheless, Samsung and Intel - Micron Flash Technologies are expected to join the fray in 2008/9 and by 2012, 3-bit per cell NAND is forecast to account for 52.8% of NAND flash memory bits, followed by MLC NAND at 25.4%, 4-bit/cell NAND 16.6% and SLC NAND 4.4%.
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