Hynix announced it has developed a 32Gb 3-bit per cell NAND flash slated for production in October. Hynix stated that the 3-bit per cell technology would enable cost reductions of 30% over 2-bit per cell technology. The 32Gb chip is based on 48nm process technology.
Based on my estimates, the die size of this device should be over 200mm2, much larger than the 172mm2 of the recently announced 34nm 32Gb MLC NAND flash from Intel/Micron. It is unlikely the chip is using the All-Bitline architecture developed by SanDisk and Toshiba implying a fairly low program performance.
The 32Gb chip will probably be employed as a learning vehicle for applications enablement until a more competitive 41nm offering comes out next year.
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I just came across your interesting blogs. What would you estimate the die size of Toshiba's recently announced 43nm 32Gb x2chip? Also, what would be your estimate for die size of Toshiba's 43nm 32Gb x3? Thanks.
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