Samsung and Numonyx today announced that they will jointly develop common specifications for phase change memory (PCM). Common specifications are necessary to drive the adoption of PCM, particularly since OEMs do not want to be beholden to one supplier. The development of common specifications is analogous to what Intel and ST did in NOR flash starting with the 90nm NOR flash generation and resulted in Intel and ST being dual sourced at major OEMs.
The bit alterability of PCM make it attractive in simplifying firmware and reducing system overhead, however, adoption of PCM will likely be limited until costs approach that of flash memories. With a 45nm 1Gb PCM chip scheduled for production for the end of 2009, Numonyx will be closing the gap with NOR flash, however it'll take much longer for a new memory technology to break out of its niche status, if at all. Just take a look at where FRAM and MRAM are today.
This colloboration is the right step to facilitate the development of the infrastructure supporting PCM. Samsung's backing is a validation of the technology and also provides OEMs the confidence to commit themselves to this emerging memory technology.
Showing posts with label phase change memory. Show all posts
Showing posts with label phase change memory. Show all posts
Tuesday, June 23, 2009
Monday, February 11, 2008
Flash Memory Replacement Achieves Major Milestones
At last week’s ISSCC, Intel and STMicroelectronics presented a paper demonstrating the first multi-level cell phase change memory [PCM]. The chip is a 256Mb device based on 90-nanometer process technology. PCM has been touted as a potential replacement for flash memory due to its fast reads and writes and superior endurance.
On the same day of the ISSCC paper, Intel and ST began shipments of prototype samples to customers of a 128Mb chip also based on the same 90nm technology. Careful reading of the ISSCC paper implies that the 256Mb MLC device and the 128Mb device are one and the same chip. The MLC technology is still in the research phase and it appears the prototype samples have the MLC functionality disabled.
The 128Mb product is mainly a learning vehicle to improve the technology for volume manufacturing, to learn about which applications may be suitable for PCM and to develop the firmware to support the devices. Due to the high initial cost of PCM, the 90nm devices will have limited production volume, however, this is expected to change as PCM migrates to more advanced process technologies and MLC technology is deployed.
PCM’s time will come as flash memory encounters scaling limitations within the next five years.
On the same day of the ISSCC paper, Intel and ST began shipments of prototype samples to customers of a 128Mb chip also based on the same 90nm technology. Careful reading of the ISSCC paper implies that the 256Mb MLC device and the 128Mb device are one and the same chip. The MLC technology is still in the research phase and it appears the prototype samples have the MLC functionality disabled.
The 128Mb product is mainly a learning vehicle to improve the technology for volume manufacturing, to learn about which applications may be suitable for PCM and to develop the firmware to support the devices. Due to the high initial cost of PCM, the 90nm devices will have limited production volume, however, this is expected to change as PCM migrates to more advanced process technologies and MLC technology is deployed.
PCM’s time will come as flash memory encounters scaling limitations within the next five years.
SanDisk's 3-Bit/Cell NAND Flash Technology Not a Short-Term Play
The development of a 16-gigabit 3-bit per cell (x3) NAND flash on 56-nanometer process technology by SanDisk and Toshiba offers the promise of further NAND flash memory cost reductions.
Due to higher design complexity, lower number of usable blocks and longer test times, x3 technology is expected to offer approximately 20% cost savings over comparable MLC devices at the same process generation.The key innovation of the x3 16Gb chip is the write performance of 8-megabytes per second (MB/s).
This outstanding performance is comparable to 5xnm MLC devices currently on the market and was enabled mainly through the development of an All Bit Line [ABL] architecture and advanced programming algorithms. ABL will also be deployed on all of SanDisk/Toshiba’s MLC devices boosting write performance to 34MB/s – comparable to SLC devices on the market.Alas, the full cost benefits of x3 won’t be realized for another two years, the reason being x3 is currently about one year behind MLC on the technology roadmap.
Nevertheless, Samsung and Intel - Micron Flash Technologies are expected to join the fray in 2008/9 and by 2012, 3-bit per cell NAND is forecast to account for 52.8% of NAND flash memory bits, followed by MLC NAND at 25.4%, 4-bit/cell NAND 16.6% and SLC NAND 4.4%.
Due to higher design complexity, lower number of usable blocks and longer test times, x3 technology is expected to offer approximately 20% cost savings over comparable MLC devices at the same process generation.The key innovation of the x3 16Gb chip is the write performance of 8-megabytes per second (MB/s).
This outstanding performance is comparable to 5xnm MLC devices currently on the market and was enabled mainly through the development of an All Bit Line [ABL] architecture and advanced programming algorithms. ABL will also be deployed on all of SanDisk/Toshiba’s MLC devices boosting write performance to 34MB/s – comparable to SLC devices on the market.Alas, the full cost benefits of x3 won’t be realized for another two years, the reason being x3 is currently about one year behind MLC on the technology roadmap.
Nevertheless, Samsung and Intel - Micron Flash Technologies are expected to join the fray in 2008/9 and by 2012, 3-bit per cell NAND is forecast to account for 52.8% of NAND flash memory bits, followed by MLC NAND at 25.4%, 4-bit/cell NAND 16.6% and SLC NAND 4.4%.
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