A New NAND Flash Player Emerges?

The U.S. Bankruptcy Court for the District of Delaware approved an agreement by Spansion’s debtors to transfer its Milan development facilities to Elpida Memory. Details of the agreement are unclear at the moment, however, Spansion will apparently retain IP rights for the technology developed at the research center.

Spansion established its Security and Advanced Technology Division (SATD) in 2007 and staffed it with ex-STMicroelectronics NAND flash engineers including division head, Carla Golla who prior to joining Spansion was the general manager of ST’s NAND Flash and Storage Media product group.

The division’s mission is to develop secure products such as the MirrorBit HD-SIM product family and ORNAND2. ORNAND2 - unlike ORNAND which is a Mirrorbit with a NAND interface – is a true NAND architecture based on SONOS technology. Spansion needed a NAND device for its MCPs and ORNAND2 was the solution which allowed Spansion to utilize its charge trap flash knowhow and sidestep IP issues related to floating gate devices. SATD was responsible for product design for ORNAND2 and the process technology was developed in the U.S.

Spansion had planned to ramp ORNAND2 into production in the second half of 2009 on 43nm with foundry partner SMIC. Needless to say, those plans were derailed with Spansion’s Chapter 11 filing.

Elpida has been a supplier of mobile DRAM to Spansion and has lost a major customer as Spansion exits the wireless market. In addition, Elpida is the only tier 1 DRAM company without NAND flash in its product portfolio. Being a second tier supplier of DRAM KGD (known good die) to NOR flash suppliers is an unenviable position. Elpida needs to capture more of the value-added and capitalize on the shift from NOR flash to NAND flash in the cellphone market.

Elpida’s newly acquired asset will allow it to do just that by leveraging SATD’s development of 1Gb-4Gb SLC NAND to offer NAND/DRAM MCP solutions. Whether the device will be SONOS or floating gate-based is not certain, however the fact that Spansion will retain partial IP ownership of SATD developments suggests at some sort of cooperation utilizing Spansion’s SONOS technology. This initial foray into low density SLC NAND may just portend even greater ambitions in the high density data storage market.

Samsung and Toshiba Extend Patent Cross-licensing Agreement

Samsung and Toshiba have decided to extend their semiconductor patent cross-licensing agreement which ran from September 2002 to March 2009. No timetable was given for the new agreement but it is estimated that it will run for seven years, the same timeframe for the earlier announced Samsung-SanDisk patent cross license agreement.

As the inventor of NAND flash memory, Toshiba has the largest portfolio of NAND flash memory patents with a couple thousand patents. Despite being the No. 2 NAND flash memory supplier, Toshiba has been at the forefront of introducing new process technologies. Its super self-aligned STI process introduced in its 90nm NAND flash products were copied by other vendors in their 70nm and 60nm processes. The company was also the first to introduce new materials for the wordline and bitline in its 56nm process, the same materials which were incorporated into Samsung's 42nm process. And the company also led the transition to 64-cell NAND strings.

By signing these agreements with Toshiba and SanDisk, Samsung continues to have access to important NAND flash process technology as well as multi-level cell flash memory design IP relevant for future NAND flash generations.

SandForce Unveils Revolutionary SSD Controller

SandForce has emerged from stealth mode and unveiled a SSD controller for enterprise and mobile applications. Key features of the SF-1000 controller include:

- Dramatically higher endurance (80x) due to extremely low write amplification – significantly lower than the WA of current SSD vendors.
- Symmetrical read/write 30k IOPS and 250MB/s sequential
- 5 year drive life with no daily write limitation for MLC SSD
- No degradation in the performance as the drive fills up
- No need for external RAM or over-provisioning thereby reducing system costs
- ECC engine and RAID configuration of flash devices provides unrecoverable BER of 10E17

Existing solutions trade performance, reliability and endurance at the expense of additional cost. SandForce's DuraClass technology offers better performance, endurance and reliability at a lower system cost and paves the way for use of MLC NAND in a tiered storage hierarchy in enterprise systems. If SandForce is able to deliver on its promises, it is a truly revolutionary technology which will help drive the adoption of SSDs in both enterprise and mobile environments.

Finally! A Simple Metric for Solid State Drive Endurance

We've all seen the impressive MTBF (mean time between failures) specifications of SSDs versus HDDs of one to two million hours versus 600 thousand hours in a notebook pc class application. However, unlike HDDs where a mechanical failure can make the entire HDD unusable, the main failure mechanism in a SSD relates to the memory cells becoming unusable. MTBF is a statistical calculation that unfortunately, does not capture the effect of write endurance.

The write endurance of a SSD is a function of the type of flash memory used (SLC, MLC), storage capacity, frequency of writes, data sizes of the writes and the amount of static data which relates to the wear leveling algorithm. System level endurance of SSDs in the industrial, enterprise and miliary space have ranged anywhere from one million to five million program/erase cycles. There are three main problems with this.

1. The endurance will depend on how the SSD is used in the application. As a result, SSD vendors can tweak the parameters for their own marketing purposes.

2. Not all SSD vendors use the same formula for calculating the endurance and the formulas can be overly complex.

3. A straight endurance metric is nebulous and difficult to grasp its implications, especially for OEMs who've never had to grapple with endurance issues in HDDs. For example: What's the effect on the lifetime of the drive?

SanDisk aims to solve this with the Longterm Data Endurance (LDE) metric. LDE is simply defined as the total amount of data writes allowed in the lifespan of the SSD. The metric is based on the Bapco write usage pattern for a typical business user and assumes the data is written equally over the lifetime of the drive and that data is retained for one year once the LDE specification is reached.

LDE allows OEMs a simple way to compare SSDs and determine, based on the applications usage patterns which drives are suitable for a particular application. For example, a drive with an 80TBW (teraByte write) LDE can support 20GB writes per day for 10 years (equivalent to 73TBW). For an application requiring support for only half the number of writes per day (10GB), a 40TBW rated drive would be sufficient.

The beauty of LDE is that it captures endurance in one single, understandable figure. A common metric is necessary to facilitate SSD adoption moving forward. Now comes the hard part: garnering support from other SSD vendors and OEMs.

I've uploaded a copy of Don Barnetson's presentation on LDE, "Solid State Drives: The MLC Challenge" on my website at http://www.forward-insights.com/.

Hynix Develops x3

Hynix announced it has developed a 32Gb 3-bit per cell NAND flash slated for production in October. Hynix stated that the 3-bit per cell technology would enable cost reductions of 30% over 2-bit per cell technology. The 32Gb chip is based on 48nm process technology.

Based on my estimates, the die size of this device should be over 200mm2, much larger than the 172mm2 of the recently announced 34nm 32Gb MLC NAND flash from Intel/Micron. It is unlikely the chip is using the All-Bitline architecture developed by SanDisk and Toshiba implying a fairly low program performance.

The 32Gb chip will probably be employed as a learning vehicle for applications enablement until a more competitive 41nm offering comes out next year.

Intel and Micron Leapfrog the Competition

Intel and Micron announced today that it will be sampling a 34nm 32Gb MLC NAND flash to customers in June with production slated for the second half of 2008. Owing to the aggressive gate half-pitch, immersion lithography with self-aligned double patterning employing spacers is most likely being used. Also expect changes in the bitline and wordline materials as well as a higher k interpoly dielectric in comparison to the 50nm generation.

At 172mm2, Intel-Micron's 32Gb product will be the only 32Gb monolithic MLC device capable of fitting in a TSOP package. If the ramp of IMFT's 50nm 16Gb device is any guide, we should expect to see volume in December or in early Q1/09. It's quite remarkable that Intel-Micron have managed to catch up and surpass the other NAND flash vendors on process technology in the short span of three years. IMFT achieved this milestone by skipping the 6xnm and 4xnm nodes. However, any cost advantage could be short-lived if IMFT fails to ramp up the technology smoothly and SanDisk/Toshiba ramps its 43nm 32Gb x3 in Q1/09 as planned.

Hynix Connects the Dots

On March 20, Nanosys, Inc. announced that Hynix Semiconductor Inc. will collaborate with Nanosys to employ Nanosys' quantum dot flash memory technologies (QDM) for NAND based flash memory. Hynix is the third major semiconductor manufacturer to sign up for access to Nanosys’ technology. Intel invested $38 million in Nanosys’ second round financing that closed in May 2003 and subsequently, announced a technical collaboration in 2004 to explore the use of nanocrystals in memory devices. In 2006, the collaboration was expanded to include Intel’s NAND flash memory partner, Micron Technology.

NAND-based nanocrystal memories can potentially provide a scaling path for current floating gate (FG) technologies by reducing the capacitive coupling between cells and eliminating SILC. The main challenge has been the controllability and uniformity of the nanocrystal size and distribution with technology scaling.
Nanosys claims to have solved this issue. Nanosys’ QDM with proprietary ligands are applied with a traditional spin-on process and self-assemble into a consistent monolayer on the wafer. The integration involves fewer process steps than either FG or nitride charge trap flash (CTF) alternatives while offering a very large voltage threshold window for enhanced MLC capability.

If QDM can deliver on its promise, we could see QDM enter into production at the 3xnm node and beyond.

Flash Memory Replacement Achieves Major Milestones

At last week’s ISSCC, Intel and STMicroelectronics presented a paper demonstrating the first multi-level cell phase change memory [PCM]. The chip is a 256Mb device based on 90-nanometer process technology. PCM has been touted as a potential replacement for flash memory due to its fast reads and writes and superior endurance.

On the same day of the ISSCC paper, Intel and ST began shipments of prototype samples to customers of a 128Mb chip also based on the same 90nm technology. Careful reading of the ISSCC paper implies that the 256Mb MLC device and the 128Mb device are one and the same chip. The MLC technology is still in the research phase and it appears the prototype samples have the MLC functionality disabled.

The 128Mb product is mainly a learning vehicle to improve the technology for volume manufacturing, to learn about which applications may be suitable for PCM and to develop the firmware to support the devices. Due to the high initial cost of PCM, the 90nm devices will have limited production volume, however, this is expected to change as PCM migrates to more advanced process technologies and MLC technology is deployed.

PCM’s time will come as flash memory encounters scaling limitations within the next five years.

SanDisk's 3-Bit/Cell NAND Flash Technology Not a Short-Term Play

The development of a 16-gigabit 3-bit per cell (x3) NAND flash on 56-nanometer process technology by SanDisk and Toshiba offers the promise of further NAND flash memory cost reductions.

Due to higher design complexity, lower number of usable blocks and longer test times, x3 technology is expected to offer approximately 20% cost savings over comparable MLC devices at the same process generation.The key innovation of the x3 16Gb chip is the write performance of 8-megabytes per second (MB/s).

This outstanding performance is comparable to 5xnm MLC devices currently on the market and was enabled mainly through the development of an All Bit Line [ABL] architecture and advanced programming algorithms. ABL will also be deployed on all of SanDisk/Toshiba’s MLC devices boosting write performance to 34MB/s – comparable to SLC devices on the market.Alas, the full cost benefits of x3 won’t be realized for another two years, the reason being x3 is currently about one year behind MLC on the technology roadmap.

Nevertheless, Samsung and Intel - Micron Flash Technologies are expected to join the fray in 2008/9 and by 2012, 3-bit per cell NAND is forecast to account for 52.8% of NAND flash memory bits, followed by MLC NAND at 25.4%, 4-bit/cell NAND 16.6% and SLC NAND 4.4%.